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Parallel Nanowire Devices for Sensing and Logic

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Fig. 1
Fig. 1: Nanowire channels with different composition and  coatings build the basis of printed sensing and logic circuits.

Functional parallel arrangements of a multitude of silicon nanowires are studied for sensing and simple logic electronic applications. Thereby the sensitive response of individual nanowires is added up to deliver transistors and transducers with high currents. In our parallel nanowire technology as-grown and processed nanowire structures are transferred to the final host substrates where transistors and sensors are built. By following this approach high temperature processes like oxidation and activation anneals can be decoupled from the host substrate. This enables the integration of nanowire devices on substrates and processed chips with low temperature budget properties. We have integrated nanowire sensors on flexible plastic substrates and in the back-end-of-line of fully processed CMOS chips.

Si and Ge nanowires can be processed with the complete metal / oxide / semiconductor stack on the temperature stable as grown substrate, see Fig. 1. The nanowires are coated with a surrounding dielectric gate stack, e.g. thermal SiO2 and ALD HfO2  for silicon and Al2O3 for germanium nanowires.

Fig. 2
Fig. 2: Doping-free CMOS technology with printed parallel nanowire channel. The technology allows reconfiguration at runtime, e.gt. between NAND and NOR functions.

 

 

In specific applications a surrounding ALD TiN coating is provided in cooperation with the cooperation partner HLT as a gate electrode. Two different methods are used for parallel array transfer. In the first one contact printing over the complete chip area transfers a sheet of roughly parallel aligned nanowires on the surface of the host substrate. We have successfully built devices on surface oxidized host Si chips and mechanically flexible plastic substrates. For logic applications we have shown a printable and doping free CMOS technology making use of our RFET concept. By this approach we have experimentally shown reconfiguration between NAND and NOR circuits at full output swing, see Fig. 2.

Fig. 3
Fig. 3: Hybrid CMOS Si nanowire sensor array chip for spaciotemporal sensing of pH and bio-species. 32x32 individually addressable sensor sites with high sensitivity of functionalized Si nanowires.

 

In the second approach we integrate a functional transducer layer on top of a completely processed CMOS chip. In this hybrid approach we combine the high sensitivity and specifity of bio-coated nanowires with a dedicated low-noise on-chip amplification circuitry. The Si nanowires are transferred and assembled selectively at the desired electrodes by dielectrophoresis. Back end compatible contacting, passivation coating procedures were developed. In cooperation with ETH and Riken a sensing chip with an array of 32x32 independent and individually addressable nanowire sensor sites was developed, Fig. 3. We have demonstrated stable spatiotemporal measurements of pH and dopamine in the femto-molar range.

 

Contact: Dr. Walter M. Weber

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