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Nanowire Based Reconfigurable Transistor

Fig. 1
Fig. 1: a) Schematic of a reconfigurale Si nanowire FET. b) TEM cross section of oxidized Si core and simulated strain distribution c) SEM image of junction: lateral nanowire heterostructure.

A promising concept to leverage computing power beyond conventional Moore´s scaling is to extend the functional diversity of the basic electronic device, the transistor. Namlab´s unique reconfigurable nanowire approach focuses on establishing a multifunctional electronics platform able to perform a higher number of functions with the same hardware complexity as conventional CMOS electronics. The reconfigurable nanowire field effect transistor (RFET) conceived at Namlab and introduced already in 2006 is a four terminal device that provides unipolar n- or p-type electrical characteristics at runtime as selected by an electric select signal, see Fig. 1. Importantly, these devices are obtained without the need for doping and can be fabricated with materials and processes established in volume silicon CMOS production facilities.To enable the demonstration of more complex circuits and to investigate integrability in modern CMOS flows we have extended our RFET technology from a bottom-up fabrication route to top-down processing based on silicon on insulator (SOI) wafers.Thereby, Namlab´s drain-current symmetry enabler by stressor shells was successfully applied ensuring complementary operation of digital circuits with low power consumption. Both, an omega gate architecture as well as a high-k metal gate surround gate geometry were studied for electrostatic enhancement.

Fig. 2
Fig. 2: Tilted SEM image of reconfigurable nanowire FET. In yellow the independent gates.



Further, the RFET concept was extended to include a higher number of independent steering gates allocated along the channel. For specific gate lengths and distinct to MOSFETs, the on-conductance does not change with additional gates.

Fig. 3
Fig. 3: Design flow with multi-independent-gated (MIG) RFETs. Example of a reconfigurable circuit with 2-XOR, 2-XNOR and 3XOR functionality. Cell layout in 22 nm FDSOI



The multi independent gate (MIG) approach efficiently bundles series chains of FETs in a single device sparing interconnects and area for isolations, contacts and wells. The MIG RFET inherently provides a wired-AND function useful in many multi-input combinational circuits.  In an additional device work and in cooperation with EPFL Prof. G. De Micheli, the transport properties of steep slope multi-gated transistors have been studied.
We have shown a comprehensive library of reconfigurable logic gates based on RFETs. Promising examples are multi-bit adders that consume smaller transistor count.  In addition critical paths are significantly reduced leading to a reduction of the overall structural delay by approximately 50%. In cooperation with cfaed circuit design has advanced to enable logic and physical synthesis of circuits built of RFETs.


Contact: Dr. Walter M. Weber


NaMLab gGmbH
Nöthnitzer Str. 64 a
01187 Dresden

Phone: +49.351.21.24.990-00
Fax: +49.351.475.83.900

info (at)



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