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High-k Dielectrics on Gallium Nitride

Fig. 1
Fig. 1: Comparison of transfer characteristic @ VDS = 5 V of MIS-HEMT with 12 nm ALD Al2O3 versus HEMT with Schottky gate. OFF-state drain current reduction by factor 1000.

The AlGaN/GaN High-Electron-Mobility Transistor (HEMT) with Schottky gate suffers from a high level of gate leakage current, which can be significantly reduced by inserting a gate dielectric for the fabrication of the so called MIS-HEMT. Based on the considerations of a high-k dielectric material with a wide bandgap and a convenient band alignment towards GaN in combination with a conformal and precise deposition technique as required for non-planar gate modules, we focused on the integration of ALD Al2O3 and HfO2 dielectric layers, into the gate module of MIS-HEMT devices. In Fig. 1 the transfer characteristic of HEMT versus MIS-HEMT with 12 nm Al2O3 is shown. The tremendous reduction in gate leakage current for the MIS-HEMT results in about 3 orders of magnitude lower drain current in OFF-state and, thus, in about the same increase in ON/OFF current ratio for the MIS-HEMT 1010 compared to the HEMT 107.

Fig. 2
Fig. 2: Threshold voltage shift upon stepped gate bias stress of 1 ms for “high-k first” vs. “high-k last” sample. Illustrative band diagram for equilibrium and spill-over case.

 

 

 

 

However, by inserting a high-k dielectric layer under the Schottky-type gate of an AlGaN/GaN HEMT, threshold voltage (Vth) instability becomes one of the major concerns of MIS-HEMTs. Trap states located at or near the additional high-k/(Al)GaN interface are the main cause of this detrimental phenomenon. Charge (de-) trapping in these defect states result in a shift of the threshold voltage, which in turn degrades device performance in switching application. NaMLab has set-up an extended analysis methodology, i.e. fast CV-measurements in the µsec-time range for Vth-extraction, in order to determine trapped charge densities by means of threshold voltage shift. Fig. 2 shows the measured shift of threshold voltage upon stepped stress bias conditions of 1 ms duration at successive higher gate voltages in on-state for different samples each with 12 nm ALD Al2O3.

Fig. 3
Fig. 3: AFM images of as-grown heterostructure surface (a)) and after lithograghic process with resist strip (b)). Sub-nm thick film of resist residues remains on surface.

 

For the “high-k first” samples, device fabrication started with different kind of wet chemical treatments followed by the high-k deposition on the as-grown heterostructure. For the “high-k last” sample, several micro-structuring processes preceded the ALD Al2O3 deposition just before gate electrode deposition. All devices exhibit a Vth shift in positive voltage direction beyond a certain stress bias voltage (spill-over voltage) indicative for electron trapping.  However, the “high-k last” sample exhibits a much enhanced Vth-shift. This degraded characteristic is mainly caused by spurious resist residues of preceded lithographic processing steps, which lower the interface quality in case of the high-k last sample. Fig. 3 shows atomic force microscopy images of an as-grown GaN-based heterostructure, representative for a clean surface, in comparison to the surface morphology after a lithographic process with resist removal, but with a sub-nanometer, thin cover of remaining resist.
Various process sequences are evaluated for further improvement.

 

Contact: Dr. Andre Wachowiak

 

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