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Gallium Nitride Based Device Technology

Fig. 1
Fig. 1:  Schottky-Gate HEMT device on GaN-Si wafer. Locations of high electric fields and various detrimental defects and traps are indicated. Background: 150 mm HEMT wafer.

The wide bandgap semiconductor GaN has superior material properties e. g. higher electric breakdown field, higher saturation velocity, compared to Si. Moreover, it allows for manufacturing a so called High-Electron-Mobility Transistor (HEMT), in which a buried two-dimensional electron gas (2DEG) at an AlGaN/GaN heterostructure interface can be controlled by means of a gate (Fig.1). Currently, GaN based power electronic devices are emerging as switching components for next generation high-efficiency power converters. The GaN-on-Si technology platform offers the best cost figures for commercialization of these products, although technologically very challenging. A complex GaN buffer for stress management and insulation purpose is required. Extended defects and impurities in the GaN based layers can cause degradation of device performance and reliability. By utilizing the HEMT technology up to 150 mm wafer diameter based on contact lithography the influence of the material quality of the GaN based layer stack on final device characteristic is investigated.

Fig. 2
Fig. 2: Left: Schematic of vertical MOSFET in GaN matrix with backside drain contact.  Right: ½ schematic of pseudo-vertical MOSFET on sapphire substrate. Bottom: SEM image of trench gate structure.

 

 

Additionally, we focus on the integration of high-k dielectric layers in the gate module of MIS-HEMT devices with very low gate leakage and high threshold voltage stability.
From a general perspective in comparison to lateral device architectures, true vertical device topologies with backside drain contact have the advantage of area efficient scaling of the breakdown voltage by increasing the thickness of the low doped n-drift region in vertical direction, an inherent physical separation of the low and high-voltage connections and more efficient thermal management. Motivated from these considerations, NaMLab is working on a vertical MOSFET concept in a GaN-matrix. The inversion-channel in the p-GaN layer is formed at the sidewalls of the trench gate (Fig. 2). The development of the process technology started with pseudo-vertical devices on sapphire substrates. The GaN material layer stack was grown by MOCVD up to the p-GaN body layer and over-grown by MBE with the topmost n+ source layer. For the gate module a combined dry and wet etch was utilized for trench formation followed by the gate dielectric (Al2O3) and electrode (TiN) deposition by means of ALD. 

Fig. 3
Fig. 3: Transfer characteristic of pseudo-vertical MOSFET at VDS=0.1 V. Drain current scaled on channel width in trench gate. True normally-off device operation with threshold voltage of 5 V is demonstrated.

 

 


The transfer characteristic in Fig. 3 demonstrates device functionality with an ON/OFF current ratio of about 106. A clear normally-off operation with a threshold voltage of about 5 V is shown, which is desired for power switching applications. Current development efforts are addressing the gate dielectric / p-GaN interface and in parallel the process technology is transferred on bulk-GaN substrates for true vertical devices.

 

Contact: Dr. Andre Wachowiak

 

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NaMLab gGmbH
Nöthnitzer Str. 64 a
01187 Dresden
Germany 

Phone: +49.351.21.24.990-00
Fax: +49.351.475.83.900

info (at) namlab.com

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